Current Issue : October - December Volume : 2020 Issue Number : 4 Articles : 5 Articles
Based on the step function and signum function, a chaotic system which can generate multiscroll chaotic attractors with arrangement\nof saddle-shapes is proposed and the stability of its equilibrium points is analyzed. The under mechanism for the\ngeneration of multiscroll chaotic attractors and the reason for the arrangement of saddle shapes and being symmetric about y-axis\nare presented, and the rule for controlling the number of scroll chaotic attractors with saddle shapes is designed. Based on the core\nchips including Altera Cyclone IV EP4CE10F17C8 Field Programmable Gate Array and Digital to Analog Converter chip\nAD9767, the peripheral circuit and the Verilog Hardware Description Language program for realization of the proposed\nmultiscroll chaotic system is constructed and some experimental results are presented for confirmation. The research result shows\nthat the occupation of multipliers and Phase-Locked Loops in Field Programmable Gate Array is zero....
Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in\naerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due\nto single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the faulttolerance\ncapability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive\narea consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and\nresource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation\nenvironment varies during the operation time span of the mission depending on the orbit and space weather conditions.\nTherefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level.\nIn this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data,\ninterprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability\nlevels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a\nlibrary of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time\ntool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation\nmodule with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on\nvarious benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled\nmultiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained\nfor our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore,\nDRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during runtime\nof an application....
Per-flow traffic measurement has emerged as a critical but challenging task in data centers\nin recent years in the face of massive network traffic. Many approximate methods have been proposed\nto resolve the existing resource-accuracy trade-off in per-flow traffic measurement, one of which is\nthe sketch-based method. However, sketches are affected by their high computational cost and low\nthroughput; moreover, their measurement accuracy is hard to guarantee under the conditions of\nchanging network bandwidth or flow size distribution. Recently, FPGAplatforms have been widely\ndeployed in data centers, as they demonstrate a good fit for high-speed network processing. In this\nwork, we aim to address the problem of per-flow traffic measurement from a hardware architecture\nperspective. We thus design SAPTM, a pipelined systolic array-like architecture for high-throughput\nper-flow traffic measurement on FPGA.We adopt memory-friendly D-left hashing in the design of\nSAPTM, which guarantees high space utilization during flow insertion and eviction, successfully\naddressing the challenge of tracking a high-speed data stream under limited memory resources on\nFPGA. Evaluations on the Xilinx VCU118 platform with real-world benchmarks demonstrate that\nSAPTM possesses high space utilization. Comparisons...........................
In the real-time position technology of underground shallow source, the signal denoising performance of wireless sensor nodes\ndirectly determines the location speed and accuracy of underground burst point. Because of the complexity and randomness of the\nunderground medium and the fact that underground explosion is a nonstationary transient process, the problems of low\nconvergence rate and poor steady-state performance of the filter exist when the existing LMS algorithm is used for signal\ndenoising. In light of the above concerns, this paper comes up with a signal denoising algorithm and hardware implementation\nmethod based on D-LMS (delay-LMS). Firstly, according to the autocorrelation function characteristic of random signal, using the\nprinciple that the autocorrelation function time delay characteristic of narrowband signal such as explosion vibration signal is\nbetter than that of wideband random signal such as ground noise, the D-LMS filter algorithm is constructed by introducing the\ntime delay parameter. Secondly, the selection method of key parameters in D-LMS hardware implementation is analyzed. Thirdly,\nthe corresponding hardware circuit is designed by FPGA, and the simulation is carried out. Numerical simulation and experimental\nverification show that compared with the existing LMS improved algorithm, the D-LMS algorithm proposed in this\npaper has higher denoising stability and better denoising effect. Compared with the signal postprocessing method based on the\nhost computer, the signal denoising speed of this method is significantly improved. This method will provide a powerful\ntheoretical method to solve the problem of high-precision and fast source positioning and provide technical support for the\ndevelopment of high-speed and real-time source positioning instruments....
This paper proposes a trifrequency reconfigurable antenna (FRA), which can work in the X-band, Ku-band, and Ka-band, by\ncontrolling only two RF MEMS switches.Theantenna element has a frequency ratio beyond 3 :1 and provides a good candidate for\nthe frequency reconfigurable antenna array, since the size of the antenna is reduced by loading multiple metal shorting holes\nbetween the antenna radiating surface and the ground plate, and the overall size is only..................
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